Yiming Zhou

Efficient Neural Network Architecuture Search and Deploy

Help designing a brand-new Neural Architecture Search algorithm called "Partial Order Pruning"

Second author of "Partial Order Pruning: for Best Speed/Accuracy Trade-off in Neural Architecture Search" accepted by CVPR2019

Achieve state-of-the-art performance on classification and segmentation on TX2 platform

Deploy PL1A model found by Partial Order Pruning on MI8(Snapdragon 845) with 69.1% Cityscapes test mIoU and 40+FPS

FPGA-based Efficient Segmentation Network Design on Self-driving Car

Design a light-weight semantic segmentation network deployed on FPGA platform

Fine-tune network structure and hyperparameters

Use knowledge distillation and pruning to simplify network, increasing backbone ImageNet accuracy 2.57%/1.09%

Achieve 93.4% mIoU on driving area and 60ms inference speed on FPGA

ResNet based FPGA CNN Accelerator Design

Replace Convolution with XNOR gate based on XNOR-Net

Use tensorflow to verify the effective of algorithm

Design Convolution Module, RAM block, Control Module and Logics in VHDL on VC707 platform

Design, Develop and Deploy of Powerline Communication System

Simulate system and blocks on Matlab

Program on TMS320F28069 DSP chip using C

Design the synchronization algorithm based on the channel character of 220V powerline